1. Technical Field
The present invention relates to a semiconductor integrated circuit device, and more particularly, to a high density semiconductor integrated circuit device capable of securing gate performance and a channel length.
2. Related Art
As integration of semiconductor memory devices increase, an area occupied by each memory cell decreases. In correspondence to the decrease in the area of the memory cell, various optimization attempts have been made, such as forming connection members for connecting a switching element, a bit line, a word line, and a capacitor in a buried type mode.
One suggestion has been a vertical channel semiconductor device in which a source and a drain of a MOS transistor used as a switching element are vertically arranged with a vertical channel.
The vertical channel MOS transistor includes a pillar which is vertical with respect to a semiconductor substrate, a gate electrode which is formed around the pillar, and a source and a drain which are formed on upper and lower ends of the gate electrode.
Such a vertical channel MOS transistor has an advantage in that the area of the vertical channel MOS transistor does not increase even when a channel length is increased. The vertical channel MOS transistor may also make use of a buried bit line.
However, since the pillar of the vertical channel MOS transistor should be formed as described above and the gate electrode should be formed to surround the outer circumference of the pillar, manufacturing processes are substantially complicated. For example, in order to form the gate electrode using the pillar, a complicated etching process is needed, and it is difficult to secure the characteristics of a transistor due to the complicated process.
Moreover, because of the small margin of a process of burying a metal bit line in a predefined space of the semiconductor substrate, contact between the metal bit line with the drain formed on the pillar becomes poor.
However, in the case where such a vertical structure is not adopted, as integration of a memory device increases, adjoining gate electrodes are likely to be influenced by one another, and since it is difficult to sufficiently secure a channel length, a short channel effect may be caused.